Publications

38 results for Sergey V. Rylov

A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology
- - Timothy O. Dickson
  - Yong Liu
  - et al.
- 2014
- CICC 2014
A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology
- - John F. Bulzacchelli
  - Christian Menolfi
  - et al.
- 2012
- IEEE JSSC
A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing driftsin 45-nm SOI CMOS technology
- - Gautam R. Gangasani
  - Chun-Ming Hsu
  - et al.
- 2012
- IEEE JSSC
A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology
- - John Bulzacchelli
  - Troy Beukema
  - et al.
- 2012
- ISSCC 2012
An 8x 10-Gb/s source-synchronous I/O system based on high-density silicon carrier interconnects
- - Timothy O. Dickson
  - Yong Liu
  - et al.
- 2012
- IEEE Journal of Solid-State Circuits
A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology
- - Gautam R. Gangasani
  - Chun-Ming Hsu
  - et al.
- 2011
- CICC 2011
An 8x10-Gb/s source-synchronous I/O system based on high-density silicon carrier interconnects
- - Timothy O. Dickson
  - Yong Liu
  - et al.
- 2011
- VLSI Circuits 2011
An adaptively pipelined mixed synchronous-asynchronous digital FIR filter chip operating at 1.3 gigahertz
- - Montek Singh
  - Jose A. Tierno
  - et al.
- 2010
- IEEE Transactions on VLSI Systems
A 5.4mW 0.0035mm² 0.48ps_rms-jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOS
- - Kyu-Hyoun Kim
  - Daniel M. Dreps
  - et al.
- 2009
- ISSCC 2009
Superconducting switching amplifiers for high speed digital data links
- - Amol Inamdar
  - Sergey Rylov
  - et al.
- 2009
- IEEE TAS