Publications

23 results for Daniel Dreps

Analysis and optimization of low-power passive equalizers for cpu-memory links
- - Ling Zhang
  - Wenjian Yu
  - et al.
- 2011
- IEEE Transactions on CPMT
IBM POWER7 processor circuit design
- - Dieter Wendel
  - John Barth
  - et al.
- 2011
- IBM J. Res. Dev
POWER7™, a highly parallel, scalable multi-core high end server processor
- - Dieter F. Wendel
  - Ron Kalla
  - et al.
- 2011
- IEEE Journal of Solid-State Circuits
A 4.5 mW/Gb/s 6.4 Gb/s 22+1-lane source synchronous receiver core with optional cleanup PLL in 65 nm CMOS
- - Robert Reutemann
  - Michael Ruegg
  - et al.
- 2010
- IEEE Journal of Solid-State Circuits
A 5.4mW 0.0035mm² 0.48ps_rms-jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOS
- - Kyu-Hyoun Kim
  - Daniel M. Dreps
  - et al.
- 2009
- ISSCC 2009
Design methodology of high performance on-chip global interconnect using terminated transmission-line
- - Yulei Zhang
  - Ling Zhang
  - et al.
- 2009
- ISQED 2009
On-chip bus signaling using passive compensation
- - Yulei Zhang
  - Ling Zhang
  - et al.
- 2008
- EPEPS 2008
Low power passive equalizer design for computer memory links
- - Ling Zhang
  - Wenjian Yu
  - et al.
- 2008
- HOTI 2008
Low power passive equalizer optimization using tritonic step response
- - Ling Zhang
  - Wenjian Yu
  - et al.
- 2008
- DAC 2008
A 2.6mW 370MHz-to-2.5GHz open-loop quadrature clock generator
- - Kyu-Hyoun Kim
  - Paul W. Coteus
  - et al.
- 2008
- ISSCC 2008