(Invited) cross-layer resilience: Challenges, insights, and the road ahead
- Eric Cheng
- Daniel Mueller-Gritschneder
- et al.
- 2019
- DAC 2019
Conference paper
Publications
9 results for Mircea Stan
Tolerating soft errors in processor cores using CLEAR (cross-layer exploration for architecting resilience)
- Eric Cheng
- Shahrzad Mirkhani
- et al.
- 2018
- IEEE TCADIS
PaperDyHard-DNN: Even more DNN acceleration with dynamic hardware reconfiguration
- Mateja Putic
- Alper Buyuktosunoglu
- et al.
- 2018
- DAC 2018
Conference paperVery low voltage (VLV) design
- Ramon Bertran
- Pradip Bose
- et al.
- 2017
- ICCD 2017
Conference paperCLEAR: Crosslayer exploration for architecting resilience combining hardware and software techniques to tolerate soft errors in processor cores
- Eric Cheng
- Shahrzad Mirkhani
- et al.
- 2016
- DAC 2016
Conference paperNear-Memory Data Services
- Babak Falsafi
- Mircea Stan
- et al.
- 2016
- IEEE Micro
ReviewScaling with design constraints: Predicting the future of big chips
- Wei Huang
- Karthick Rajamani
- et al.
- 2011
- IEEE Micro
PaperStructured and tuned array generation (STAG) for high-performance random logic
- Matthew M. Ziegler
- Gary S. Ditlow
- et al.
- 2007
- GLSVLSI 2007
Conference paperMulti-dimensional circuit and micro-architecture level optimization
- Qi Zhenyu
- Matthew Ziegler
- et al.
- 2007
- ISQED 2007
Conference paper