Publications

31 results for Stephen Kosonocky

Reducing ground-bounce noise and stabilizing the data-retention voltage of power-gating structures
- - Suhwan Kim
  - Chang Jun Choi
  - et al.
- 2008
- IEEE Transactions on Electron Devices
A sub-600-mV, fluctuation tolerant 65-nm CMOS SRAM array with dynamic cell biasing
- - Azeez J. Bhavnagarwala
  - Stephen Kosonocky
  - et al.
- 2008
- IEEE Journal of Solid-State Circuits
A sub-600mV, fluctuation tolerant 65nm CMOS SRAM array with dynamic cell biasing
- - Azeez Bhavnagarwala
  - Stephen Kosonocky
  - et al.
- 2007
- VLSI Circuits 2007
Structured and tuned array generation (STAG) for high-performance random logic
- - Matthew M. Ziegler
  - Gary S. Ditlow
  - et al.
- 2007
- GLSVLSI 2007
Multi-dimensional circuit and micro-architecture level optimization
- - Qi Zhenyu
  - Matthew Ziegler
  - et al.
- 2007
- ISQED 2007
A multi-mode power gating structure for low-voltage deep-submicron CMOS ICs
- - Suhwan Kim
  - Stephen V. Kosonocky
  - et al.
- 2007
- IEEE TCAS-II
On-chip synchronous communication between clock domains with quotient frequencies
- - V. Sathe
  - M.C. Papaefthymiou
  - et al.
- 2007
- Electronics Letters
A 3-transistor DRAM cell with gated diode for enhanced speed and retention time
- - Wing K. Luk
  - Jin Cai
  - et al.
- 2006
- VLSI Circuits 2006
The design and implementation of a low-overhead supply-gated SRAM
- - J.B. Kuang
  - Hung Ngo
  - et al.
- 2006
- ESSCIRC 2006
Scalability options for future SRAM memories
- - Stephen V. Kosonocky
  - Azeez Bhavnagarwala
  - et al.
- 2006
- ICSICT 2006