PD/SOI SRAM performance in presence of gate-to-body tunneling current
- Rajiv V. Joshi
- Ching-Te Chuang
- et al.
- 2003
- IEEE Transactions on VLSI Systems
Paper
Publications
31 results for F. Assaderaghi
Silicon-on-insulator dynamic threshold ESD networks and active clamp circuitry
- S. Voldman
- D. Hui
- et al.
- 2002
- Journal of Electrostatics
PaperEffects of gate-to-body tunneling current on PD/SOI CMOS SRAM
- R.V. Joshi
- C.T. Chuang
- et al.
- 2001
- VLSI Technology 2001
Conference paperTheoretical determination of the temporal and spatial structure of α-particle induced electron-hole pair generation in silicon
- Phil Oldiges
- Robert Dennard
- et al.
- 2000
- IEEE TNS
PaperControlling floating-body effects for 0.13μm and 0.10μm SOI CMOS
- S.K.H. Fung
- N. Zamdmer
- et al.
- 2000
- IEDM 2000
Conference paperSilicon-on-insulator dynamic threshold ESD networks and active clamp circuitry
- S. Voldman
- D. Hui
- et al.
- 2000
- EOS/ESD 2000
Conference paperSOI at IBM: Current status of technology, modeling, design, and the outlook for the 0.1 μm generation
- F. Assaderaghi
- G. Shahidi
- 2000
- IEEE International SOI Conference 2000
Conference paperPartially depleted silicon-on-insulator (SOI): A device design/modeling and circuit perspective
- F. Assaderaghi
- G. Shahidi
- et al.
- 2000
- ICM 2000
Conference paperDesign of a high performance PD SOI for the 0.18 μm technology generation
- M. Sherony
- S.-H. Lo
- et al.
- 2000
- ICM 2000
Conference paperDTMOS: Its derivatives and variations, and their potential applications
- F. Assaderaghi
- 2000
- ICM 2000
Conference paper