Publications

15 results for W. Reohr

A 45 nm SOI embedded DRAM macro for the POWER™ processor 32 MByte on-chip L3 cache
- - John Barth
  - Don Plass
  - et al.
- 2011
- IEEE Journal of Solid-State Circuits
Statistical yield analysis of silicon-on-insulator embedded DRAM
- - R. Kanj
  - R.V. Joshi
  - et al.
- 2009
- ISQED 2009
A 1 MB cache subsystem prototype with 1.8 ns embedded DRAMs in 45 nm SOI CMOS
- - Peter J. Klim
  - John Barth
  - et al.
- 2009
- IEEE Journal of Solid-State Circuits
An on-chip dual supply charge pump system for 45nm PD SOI eDRAM
- - J.B. Kuang
  - A. Mathews
  - et al.
- 2008
- ESSCIRC 2008
A one MB cache subsystem prototype with 2GHz embedded DRAMs in 45nm SOI CMOS
- - Peter Klim
  - John Barth
  - et al.
- 2008
- VLSI Circuits 2008
Rethinking refresh: Increasing availability and reducing power in dram for cache applications
- - Philip G. Emma
  - William R. Reohr
  - et al.
- 2008
- IEEE Micro
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier
- - John Barth
  - William R. Reohr
  - et al.
- 2008
- IEEE Journal of Solid-State Circuits
A 500MHz random cycle 1.5ns-latency, SOI embedded DRAM macro featuring a 3T micro sense amplifier
- - John Barth
  - William Reohr
  - et al.
- 2007
- ISSCC 2007
Memories: Exploiting them and developing them
- - William Robert Reohr
- 2006
- SOCC 2006
A High-Speed 128-kb MRAM Core for Future Universal Memory Applications
- - John DeBrosse
  - Dietmar Gogl
  - et al.
- 2004
- IEEE Journal of Solid-State Circuits