Publications

15 results for Scott C. Lewis

Fully On-Chip MAC at 14 nm Enabled by Accurate Row-Wise Programming of PCM-Based Weights and Parallel Vector-Transport in Duration-Format
- - Pritish Narayanan
  - Stefano Ambrogio
  - et al.
- 2021
- IEEE T-ED
Fully on-chip MAC at 14nm enabled by accurate row-wise programming of PCM-based weights and parallel vector-transport in duration-format
- - P. Narayanan
  - S. Ambrogio
  - et al.
- 2021
- VLSI 2021
Circuit techniques for efficient acceleration of deep neural network inference with Analog-AI (Invited)
- - Kohji Hosokawa
  - Pritish Narayanan
  - et al.
- 2021
- ISCAS 2021
On-Chip Trainable 1.4M 6T2R PCM Synaptic Array with 1.6K Stochastic LIF Neurons for Spiking RBM
- - Masatoshi Ishii
  - U. Shin
  - et al.
- 2019
- IEDM 2019
AI hardware acceleration with analog memory: Microarchitectures for low energy at high speed
- - H. Y. Chang
  - Geoffrey W. Burr
  - et al.
- 2019
- IBM J. Res. Dev
Neuromorphic devices and architectures for next-generation cognitive computing
- - Geoffrey W. Burr
  - Pritish Narayanan
  - et al.
- 2017
- ISCAS 2017
Toward on-chip acceleration of the backpropagation algorithm using nonvolatile memory
- - Pritish Narayanan
  - Alessandro Fumarola
  - et al.
- 2017
- IBM J. Res. Dev
Neuromorphic technologies for next-generation cognitive computing
- - Robert M. Shelby
  - Pritish Narayanan
  - et al.
- 2017
- EDTM 2017
A Double-Data-Rate 2 (DDR2) Interface Phase-Change Memory with 533MB/s Read-Write Data Rate and 37.5ns Access Latency for Memory-Type Storage Class Memory Applications
- - H. Lung
  - C. Miller
  - et al.
- 2016
- IMW 2016
NVM neuromorphic core with 64k-cell (256-by-256) phase change memory synaptic array with on-chip neuron circuits for continuous in-situ learning
- - Sangbum Kim
  - Masatoshi Ishii
  - et al.
- 2015
- IEDM 2015