Publications

13 results for Dan Mocuta

Advanced metallization developments for 32-nm node CMOS technology contact architecture
- - Doug H. Lee
  - Valli Arunachalam
  - et al.
- 2009
- ADMETA 2009
High performance 32nm SOI CMOS with high-k/metal gate and 0.149μm ² SRAM and ultra low-k back end with eleven levels of copper
- - B. Greene
  - Q. Liang
  - et al.
- 2009
- VLSI Technology 2009
Extending dual stress liner process to high performance 32nm node SOI CMOS manufacturing
- - M. Cai
  - B. Greene
  - et al.
- 2008
- IEEE International SOI Conference 2008
High-performance nMOSFET with in-situ phosphorus-doped embedded Si:C (ISPD eSi:C) source-drain stressor
- - B. Yang
  - R. Takalkar
  - et al.
- 2008
- IEDM 2008
Recent progress and challenges in enabling embedded Si:C technology
- - B. Yang
  - Z. Ren
  - et al.
- 2008
- ECS Meeting 2008
RTA-driven intra-die variations in stage delay, and parametric sensitivities for 65nm technology
- - I. Ahsan
  - N. Zamdmer
  - et al.
- 2006
- VLSI Technology 2006
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- - E. Leobandung
  - H. Nayakama
  - et al.
- 2005
- VLSI Technology 2005
High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL
- - W.-H. Lee
  - A. Waite
  - et al.
- 2005
- IEDM 2005
Performance comparison and channel length scaling of strained Si FETs on SiGe-on-insulator (SGOI)
- - J. Cai
  - K. Rim
  - et al.
- 2004
- IEDM 2004
Retardation of arsenic diffusion in silicon-germanium by co-implantation
- - Omer Dokumaci
  - Paul Ronsheim
  - et al.
- 2004
- ECS Meeting 2004