A high performance 90 nm SOI technology with 0.992 μm2 6T-SRAM cell
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- 2002
- IEDM 2002
Conference paper
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17 results for P.A. McFarland
Two-dimensional profiling of shallow junctions in Si metal-oxide-semiconductor structures using scanning tunneling spectroscopy and transmission electron microscopy
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- 1996
- Journal of Applied Physics
PaperCMOS scaling in the 0.1-μm, 1.X-volt regime for high-performance applications
- G. Shahidi
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- IBM J. Res. Dev
PaperA Room Temperature 0.1 µm CMOS on SOI
- Ghavam G. Shahidi
- Carl A. Anderson
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- 1994
- IEEE Transactions on Electron Devices
PaperMaterial development of SIMOX with a thin box
- D.K. Sadana
- H.J. Hovel
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- 1993
- IEEE International SOI Conference 1993
Conference paperA high performance 0.15 μm CMOS
- G. Shahidi
- J. Warnock
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- 1993
- VLSI Technology 1993
Conference paperA room temperature 0.1 μm CMOS on SOI
- G. Shahidi
- C. Blair
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- 1993
- VLSI Technology 1993
Conference paperHigh-Performance Devices for a 0.15-μm CMOS Technology
- G. Shahidi
- James Warnock
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- 1993
- IEEE Electron Device Letters
PaperA high performance BiCMOS technology using 0.25 μm CMOS and double poly 47 GHz bipolar
- G. Shahidi
- J. Warnock
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- 1992
- VLSI Technology 1992
Conference paperMetal Migration into Polysilicon Emitter After Very High Current Stress
- Denny D. Tang
- Catherine Wong
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- 1992
- IEEE Electron Device Letters
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