High-density reduced-stack logic circuit techniques using independent-gate controlled double-gate devices
- Meng-Hsueh Chiang
- Keunwoo Kim
- et al.
- 2006
- IEEE Transactions on Electron Devices
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136 results for C.T. Chuang
Novel high-density low-power logic circuit techniques using DG devices
- Meng-Hsueh Chiang
- Keunwoo Kim
- et al.
- 2005
- IEEE Transactions on Electron Devices
Off-state current and performance analysis for double-gate CMOS with non-self-aligned back gate
- Keunwoo Kim
- Hussein I. Hanafi
- et al.
- 2005
- IEEE Transactions on Electron Devices
Leakage power analysis of 25-nm double-gate CMOS devices and circuits
- Keunwoo Kim
- Koushik K. Das
- et al.
- 2005
- IEEE Transactions on Electron Devices
A floating-body charge monitoring technique for partially depleted SOI technology
- J.B. Kuang
- M.J. Saccamango
- et al.
- 2004
- International Journal of Electronics
Compact modeling methodology of strained-Si channel-on-insulator (SSOI) MOSFETs
- Keunwoo Kim
- Ching-Te Chuang
- et al.
- 2004
- International Journal of Electronics
Process/physics-based threshold voltage model for nano-scaled double-gate devices
- Keunwoo Kim
- Jerry G. Fossum
- et al.
- 2004
- International Journal of Electronics
Performance assessment of scaled strained-Si channel-on-insulator (SSOI) CMOS
- Keunwoo Kim
- Ching-Te Chuang
- et al.
- 2004
- Solid-State Electronics
Scaling planar silicon devices
- Ching-Te Chuang
- Kerry Bernstein
- et al.
- 2004
- IEEE Circuits and Devices Magazine
Turning silicon on its edge
- Edward J. Nowak
- Ingo Aller
- et al.
- 2004
- IEEE Circuits and Devices Magazine