Scannable pulse-to-static conversion register array for self-timed circuits
- Wei Hwang
- Rajiv V. Joshi
- et al.
- 2000
- IEEE Journal of Solid-State Circuits
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42 results for W. Hwang
Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability
- Wei Hwang
- George Diedrich Gristede
- et al.
- 1999
- IEEE Journal of Solid-State Circuits
A 500-MHz, 32-word x 64-bit, eight-port self-resetting CMOS register file
- Wei Hwang
- Rajiv V. Joshi
- et al.
- 1999
- IEEE Journal of Solid-State Circuits
Implementation of a high speed multiport register file in a 1.8V, 0.25 μm CMOS bulk and SOI technology
- R.V. Joshi
- W. Hwang
- et al.
- 1999
- International Symposium on VLSI Technology, Systems, and Applications, Proceedings
Design and implementation of differential cascode voltage switch with pass-gate (DCVSPG) logic for high-performance digital systems
- Fang-Shi Lai
- Wei Hwang
- 1997
- IEEE Journal of Solid-State Circuits
Large-Signal 2T, 1C DRAM Cell: Signal and Layout Analysis
- W.H. Henkels
- W. Hwang
- 1994
- IEEE Journal of Solid-State Circuits
A 12-ns Low-Temperature DRAM
- Walter H. Henkels
- Nicky C. C. Lu
- et al.
- 1989
- IEEE T-ED
A 22-ns 1-Mbit CMOS High-Speed DRAM with Address Multiplexing
- Nicky C.C. Lu
- Gary B. Bronner
- et al.
- 1989
- IEEE Journal of Solid-State Circuits
A 20-ns 128-Kbit X 4 High-Speed DRAM with 330-Mbit/s Data Rate
- Nicky C.C. Lu
- Hu H. Chao
- et al.
- 1988
- IEEE Journal of Solid-State Circuits
Highspeed Sensing Scheme for CMOS DRAM's
- Sang H. Dhong
- Nicky Chau-Chun Lu
- et al.
- 1988
- IEEE Journal of Solid-State Circuits