Josephson 4 K-bit cache memory design for a prototype signal processor. I. General overview
- W.H. Henkels
- L.M. Geppert
- et al.
- 1985
- Journal of Applied Physics
Paper
Publications
6 results for J. Kadlec
Josephson 4 K-bit cache memory design for a prototype signal processor. III. Decoding, sensing, and timing
- W.H. Henkels
- L.M. Geppert
- et al.
- 1985
- Journal of Applied Physics
PaperJosephson 4 K-bit cache memory design for a prototype signal processor. II. Cell array and drivers
- W.H. Henkels
- L.M. Geppert
- et al.
- 1985
- Journal of Applied Physics
PaperNoise margins for Josephson logic and memory devices
- J. Kadlec
- 1983
- IEEE Transactions on Magnetics
PaperTunable Low-Loss UHF Circulator for Cryogenic Applications
- Jarda Kadlec
- 1982
- IEEE T-MTT
PaperDetermination of the dispersion relation in tunnel structures: Influence of the barrier shape and validity of the WKB approximation
- K.H. Gundlach
- J. Kadlec
- 1973
- Solid-State Electronics
Paper