Maico Cassel Dos Santos, Tianyu Jia, et al.
ISSCC 2024
This paper presents a new approach to global clock distribution in which tree-driven grids are augmented with on-chip spiral inductors to resonate the clock capacitance. In this scheme, the energy of the fundamental frequency resonates between electric and magnetic forms, with the reduced admittance of the clock network allowing for significantly lower gain requirements in the buffering network. The substantial improvements in jitter and power resulting from this approach are presented using measurement results from two test chips, one fabricated in a 90-nm and the other in a 0.18-μm CMOS technology.
Maico Cassel Dos Santos, Tianyu Jia, et al.
ISSCC 2024
Phillip J. Restle, Timothy G. McNamara, et al.
IEEE Journal of Solid-State Circuits
Phillip J. Restle, Craig A. Carter, et al.
Digest of Technical Papers-IEEE International Solid-State Circuits Conference
Brian Vanderpool, Phillip J. Restle, et al.
IEEE JSSC