A file-based adaptive prefetch caching design
F.Warren Shih, Tze-Chiang Lee, et al.
ICCD 1990
The development and comparison of two trace-driven simulation models for microsystems with tightly coupled, shared-bus multiprocessors is presented. One model monitors the complete activities of processors, private caches, global bus, and main memory, while the other first abstracts local bus activities of processors, and then takes care of the multiprocessing interaction. The second model provides a means to move more quickly within the design space, while the first model can be used to select a final optimized design. Examples are presented to illustrate how these simulation models can help a complex choice among architectures, system configurations, and chip parameters for the design of an optimized microsystem.
F.Warren Shih, Tze-Chiang Lee, et al.
ICCD 1990
F.Warren Shih, H.H. Chao, et al.
IEEE ITC 1985
H.H. Chao, Shauchi Ong, et al.
CICC 1985
C.C. Chi, D. Grischkowsky
ICCD 1987