SOI-optimized 64-bit high-speed CMOS adder design
Jae-Joon Kim, Rajiv Joshi, et al.
VLSI Circuits 2002
A number of researchers described a mixture importance sampling (MixIS) methodology to enable yield-driven design and extends its application beyond memories to peripheral circuits and logic blocks. The sampling methodology was developed by researchers as a fast Monte Carlo technique developed for memory analysis. The MixIS was a comprehensive and computationally efficient method of estimating low failure probabilities of SRAM designs. This method relied on distorting the Monte Carlo sampling function to produce more samples in the important regions and rare-failure-event critical regions. The MixIS methodology was universal and its efficiency was independent of the underlying technology or application. The methodology was also used to compare two different local bit-select circuits in 45-nm technology.
Jae-Joon Kim, Rajiv Joshi, et al.
VLSI Circuits 2002
Rouwaida Kanj, Rajiv Joshi, et al.
DAC 2006
Maria Malik, Rajiv V. Joshi, et al.
IEEE Transactions on VLSI Systems
Vinod Ramadurai, Rajiv Joshi, et al.
CICC 2007