Tobias Webel, Phillip J. Restle, et al.
IEEE Journal of Solid State Circuits
Paper
The clock distribution of the Power4 microprocessor
Abstract
The clock distribution of the Power4 microprocessor was studied. This distribution on the Power4 supplies a single critical 1.5 GHz clock from one SOI-optimized phase locked loop (PLL) to 15,200 pins on a large chip with 20 ps skew and 35 ps jitter. The network contains 64 tuned trees driving a single grid, and specialized tools to achieve targets on schedule with no adjustment circuitry.
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IEEE Journal of Solid-State Circuits
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A shorted global clock design for multi-GHz 3D stacked chips
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Phillip J. Restle, Timothy G. McNamara, et al.
IEEE Journal of Solid-State Circuits