Koushik K. Das, Shih-Hsien Lo, et al.
IEEE International SOI Conference 2004
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Sub-15 ps charge-buffered active-pull-down ECL/NTL circuits
Abstract
ECL/NTL circuits with charge-buffered active-pull-down configuration are described. Implemented in a 0.8 μm double-poly trench-isolated self-aligned bipolar process, unloaded gate delays of 14.9-ps/2.2-mW and 12.8-ps/1.0-mW have been achieved for the charge-buffered active-pull-down ECL and NTL circuit, respectively. © 1992 IEEE.
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