Conference paper
Effect of the back gate conduction on 0.25 μm SOI devices
J.L. Pelloie, D.K. Sadana, et al.
IEDM 1994
A new technology is presented for in-trench device fabrication using selective epitaxial overgrowth and preferential polishing. The silicon quality is investigated by a comparison of diodes in the centre of the trench, butted to the sides and overlapping the entire trench area. Good results were obtained for centre and butted devices. Ideal characteristics were found also for the overlap diodes, but with lower yield. © 1989, The Institution of Electrical Engineers. All rights reserved.
J.L. Pelloie, D.K. Sadana, et al.
IEDM 1994
C.T. Chuang, J.D. Cressler, et al.
Electronics Letters
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