Plate-Noise Analysis of an On-Chip Generated Half-VDD Biased-Plate PMOS Cell in CMOS DRAM's

This paper reports a detailed plate-noise analysis on using an on-chip generated half-VDD bias for the memory-cell plate in CMOS DRAM's to reduce the electric field in the storage capacitor insulator, in contrast to the VDD-biased or grounded cell plate generally used in NMOS DRAM's. The detailed design of a half-VDD biased-plate PMOS cell in n-well CMOS is described. © 1985 IEEE