Impact of conductance drift on multi-PCM synaptic architectures
Irem Boybat, S. R. Nandakumar, et al.
NVMTS 2018
This work presents the design and the silicon implementation of an on-line energy optimizer unit based on novel analog computation approaches, which is capable of dynamically adjusting power supply voltages and operating frequencies of multiple processing elements on-chip. The optimized voltage/frequency assignments are tailored to the instantaneous workload information on multiple tasks and fully adaptive to variations in process and temperature. The optimizer unit has a response time of less than 50 μs, occupies a silicon area of 0.021 mm2/task and dissipates 2 mW/task. © 2007 IEEE.
Irem Boybat, S. R. Nandakumar, et al.
NVMTS 2018
Lukas Kull, Thomas Toifl, et al.
ISSCC 2013
Thomas Brunschwiler, Stephan Paredes, et al.
ITherm 2010
Stanislaw Wozniak, Angeliki Pantazi, et al.
IJCNN 2017