Conference paper
On the dynamic resistance and reliability of phase change memory
B. Rajendran, M.H. Lee, et al.
VLSI Technology 2008
A novel Pillar phase change memory based on fully integrated test arrays in 180nm CMOS technology has been successfully fabricated. A current-confining Pillar structure leads to a self-heating at the center of the chalcogenide layer, and needs only one additional mask level for its fabrication. Switching characteristics with write currents less than 900μA at 75nm diameter and multilevel operation are reported. © 2006 IEEE.
B. Rajendran, M.H. Lee, et al.
VLSI Technology 2008
Chin-An Chang, Yong-Kil Kim, et al.
Journal of Vacuum Science and Technology A: Vacuum, Surfaces and Films
Y.H. Shih, J.Y. Wu, et al.
IEDM 2008
Yong-Kil Kim, Chin-An Chang, et al.
Journal of Applied Physics