Model for a 15ns 16K RAM with Josephson junctions

R.F. Broom; P. Gueret; W. Kotyczka; T. Mohr; A. Moser; A. Oosenbrug; P. Wolf

doi:10.1109/ISSCC.1978.1155788

ISSCC 1978

Conference paper

15 Feb 1978

Model for a 15ns 16K RAM with Josephson junctions

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Abstract

A RAM cross section, intended as a feasibility model for a 16K bit memory with an access time of approximately 15ns, has been developed. The design, including array, drivers and decoders, will be described and test results offered.

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