Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design

This paper presents mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuits for low-power, high performance and deep- submicron VLSI design. These logic circuits incorporate two different sets of CMOS devices, low-Vt and regular high-Vt CMOS devices. By appropriately selecting the low-Vt and high-Vt devices and configurations in a circuit, we can gain performance of circuit while keeping the leakage current and power low. The key approaches are using low-Vt devices to gain performance, using high-Vt devices to cut off the leakage path and also using the reverse- biased low-Vt devices in their standby state. The methodology and algorithm are developed and simulated. The applications of such multi-Vt circuit techniques to the static, domino NORA DCVS and delayed reset circuits are described. The use of footer / header devices, gated-Vdd and a mixture of low-Vt and high-Vt devic es to reduce power dissipation and subthreshold leakage current during standby and active modes, and the global design issues are also discussed.