Jessica Gruss-Gifford, T. Haigh, et al.
ASMC 2018
As integrated circuits for high performance CMOS devices scale down to = 10 nm dimension, further reductions in cap thickness to reduce capacitance are required for the Cu barrier while maintaining sufficient mechanical strength, low leakage, high dielectric breakdown, and fabrication integration robustness. This paper presents the development of a second generation robust low-hydrogen SiCN films to enable cap thickness reduction to = 10 nm by simply altering/reducing the hydrogen concentration in the SiCN film. This is achieved by the simple addition of hydrogen precursor in the plasma deposition chemistry.
Jessica Gruss-Gifford, T. Haigh, et al.
ASMC 2018
Daniel C. Edelstein, M. Rizzolo, et al.
IEDM 2020
Kangguo Cheng, Chanro Park, et al.
VLSI Technology 2020
Takeshi Nogami, Raghuveer Patlolla, et al.
IITC 2017