Implementation challenges for scalable neuromorphic computing
Shintaro Yamamichi, Akihiro Horibe, et al.
VLSI Technology 2017
We report the fabrication of short-channel FinFETs on InGaAs-on-silicon wafers using the aspect ratio trapping (ART) technique. We demonstrate excellent short-channel control down to 20 nm gate length due to scaled fin width down to 9 nm and reduction of parasitic bipolar effect (PBE). PBE that plagues III-V NFETs with gate-all-around (GAA) or III-V-on-insulator (III-V-OI) structures can be significantly suppressed by optimized ART FinFET technology. We demonstrate record high on-current ION and low drain leakage current for short gate lengths in the 20-32 nm range for InGaAs-on-silicon NFETs.
Shintaro Yamamichi, Akihiro Horibe, et al.
VLSI Technology 2017
Sae Kyu Lee, Ankur Agrawal, et al.
IEEE JSSC
Guohan Hu, D. Kim, et al.
IEDM 2019
Sufi Zafar, Christopher P. D’Emic, et al.
ACS Nano