Conference paper
A shorted global clock design for multi-GHz 3D stacked chips
Liang-Teck Pang, Phillip J. Restle, et al.
VLSI Circuits 2012
Fixed- and variable-length ring oscillators (RO's) are designed for characterization of circuit-topology induced variations and spatial correlations. A 930μm × 775μm test array is implemented in a low-power 45nm CMOS process. Measurements from the fixed-length RO's quantify an increase in variability with transistor stack height in logic gates and added variability associated to the top transistor in the stack. In addition, Variable-length RO's (VRO's) are designed to measure spatial correlation with a single-gate resolution. © 2009 IEEE.
Liang-Teck Pang, Phillip J. Restle, et al.
VLSI Circuits 2012
Borivoje Nikolić, Ji-Hoon Park, et al.
IEEE TCAS-I
Jason Tsai, Seng Oon Toh, et al.
ISSCC 2010
Ching Zhou, Bruce M. Fleischer, et al.
CICC 2009