Compact modeling of stress effects in scaled CMOS
Chi-Chao Wang, Wei Zhao, et al.
SISPAD 2009
In this paper, a new approach of transistor modeling is developed for fast statistical circuit simulation in the presence of variations. For both the I-V and C-V characteristics of a transistor, finite data points are identified based on their physical meanings and their importance in circuit operation. The impact of process and design variations is embedded into these key points using analytical expressions. During the simulation, the entire I-V and C-V curves are interpolated from these points with simple polynomial formulas. This novel approach significantly enhances the simulation speed with sufficient accuracy. The model is implemented in Verilog-A to support generic circuit simulators. The accuracy and convergence of the proposed model are comprehensively evaluated through a set of benchmark circuits, including nand, a pass-gate, latches, AOI, ring oscillators, and an adder. Compared to SPICE simulations with the BSIM models, the simulation time can be reduced by 7 × in transient analysis and more than 9 × in Monte-Carlo simulations. © 2006 IEEE.
Chi-Chao Wang, Wei Zhao, et al.
SISPAD 2009
Chi-Chao Wang, Wei Zhao, et al.
ICCAD 2009
Wei Zhao, Frank Liu, et al.
IEEE Trans Semicond Manuf
Duane Boning, Joseph Panganiban, et al.
TAU 2002