CMOS-on-SOI ESD protection networks

S. Voldman; R. Schulz; J. Howard; V. Gross; S. Wu; A.S. Yapsir; D.K. Sadana; H.J. Hovel; J. Walker; F. Assaderaghi; B. Chen; J.Y.-C. Sun; G. Shahidi

doi:10.1016/S0304-3886(97)00156-3

Journal of Electrostatics

Paper

01 Jan 1998

CMOS-on-SOI ESD protection networks

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Abstract

ESD robustness of 4 kV HBM is achieved in CMOS-on-SOI ESD protection networks in an advanced sub-0.25 μm mainstream CMOS-on-SOI technology. Design layout, body contact, floating-gate effects and novel ESD protection implementations are discussed. © 1998 Elsevier Science B.V.

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