Architecture and VLSI module generator for expressing digital signals in decibels

An architecture and automatic parametric VLSI design for expressing digital signals in decibels is presented. Both the piece-wise linear approximation and a look-up table ROM was used to compute the logarithm involved. The round-off error analysis is also given and the optimal wordlength of the various sections of the hardware for all input/output requirements is described. A module generator implementing the simplified architecture is presented, it is independent of technology and design rules, accepts any standard cell library, has a wide range of parameters, is easy to use and can be readily interfaced to other CAD tools. © 1991 Taylor & Francis, Ltd.