Conference paper
Full metal gate with borderless contact for 14 nm and beyond
Soon-Cheon Seo, L.F. Edge, et al.
VLSI Technology 2011
Detailed analysis of a buried layer of GaAs in 〈100〉 Si was carried out using electron energy loss spectroscopy, Rutherford backscattering spectroscopy, and ion channeling. The layer was formed by 200 keV dual ion implantation of Ga plus As ions, followed by furnace annealing at 600 and 950°C. It consists of GaAs particles which are surrounded by fully recrystallized silicon. Beneath it is a dislocation network, made up of a mixture of edge and screw dislocations.
Soon-Cheon Seo, L.F. Edge, et al.
VLSI Technology 2011
Hiroaki Arimura, Stephen L. Brown, et al.
IEEE Electron Device Letters
Chiara Marchiori, Martin M. Frank, et al.
Applied Physics Letters
Ryosuke Iijima, Lisa F. Edge, et al.
Japanese Journal of Applied Physics