A 2-ns Cycle, 3.8-ns Access 512-kb CMOS ECL SRAM with a Fully Pipelined Architecture

This paper describes a 512K CMOS SRAM with ECL interfaces which has a 2-ns cycle time and a 3.8-ns access time, both of which are valid for random read/write operations. The 2-ns cycle time is achieved without degrading access time or operating margins by using a fully pipelined architecture incorporating self-resetting circuit blocks. The CMOS process features a 0.8-μm average feature size, self-aligned TiSi, triple-level metal, and a 0.5-μm L. Details of the pipelined architecture are described along with several examples of the self-resetting circuit blocks with emphasis on features key to high-speed operation, fast cycle time, and robust design. © 1991 IEEE