Mix-and-match considerations for EUV insertion in N7 HVMXuemei ChenAllen Gaboret al.2017SPIE Advanced Lithography 2017
Single-expose patterning development for EUV lithographyAnuja De SilvaKaren Petrilloet al.2017SPIE Advanced Lithography 2017
Directed self-assembly patterning strategies for phase change memory applicationsRobert L. BruceGloria Fraczaket al.2017SPIE Advanced Lithography 2017
Printability and actinic AIMS review of programmed mask blank defectsErik VerduijnPawitter Mangatet al.2017SPIE Advanced Lithography 2017
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channelsRuilong XiePietro Montaniniet al.2016IEDM 2016
Design technology co-optimization assessment for directed self-Assembly-based lithography: Design for directed self-Assembly or directed self-Assembly for designKafai LaiChi Chun Liuet al.2017J. Micro/Nanolithogr. MEMS MOEMS
Study of alternate hardmasks for extreme ultraviolet patterningAnuja De SilvaIndira Seshadriet al.2016JVSTB
FINFET technology featuring high mobility SiGe channel for 10nm and beyondDechao GuoG. Karveet al.2016VLSI Technology 2016
Detection of printable EUV mask absorber defects and defect adders by full chip optical inspection of EUV patterned wafersLuciana MeliScott D. Halleet al.2016ASMC 2016
Lithographic qualification of high-Transmission mask blank for 10nm node and beyondYongan XuTom Faureet al.2016SPIE Advanced Lithography 2016
IBM and Albany partners unlock new yield benchmarks for EUV patterningTechnical noteLuciana Meli and Nelson Felix24 Oct 2024Semiconductors
EUV patterning yield breakthrough sets new benchmark for logic scalingTechnical noteNelson Felix and Luciana Meli06 Nov 20204 minute readAI HardwareHardware TechnologyLogic ScalingSemiconductors
IBM Research at SPIE 2020: New architectures and fabrications for AI hardwareResearchNelson Felix21 Feb 20204 minute readAI HardwareSemiconductors