Masatoshi Ishii

Title

Research Scientist

Bio

Masatoshi Ishii is a Research Scientist at IBM Research – Tokyo. He joined IBM in 1998 and has worked across a wide range of electrical engineering fields, including full-custom SRAM circuit design, HDL-based digital circuit design, FPGA-based chip evaluation, wafer testing, signal and power integrity analysis, and printed circuit board design. His current research focuses on architectures and circuits leveraging emerging memory technologies, as well as the development of energy-efficient computing architectures.

ORCID: 0000-0003-0794-7232
Google Scholar: zQqKuIEAAAAJ

Publications

Architectures and Circuits for Analog-memory-based Hardware Accelerators for Deep Neural Networks
- - Sidney Tsai
  - Pritish Narayanan
  - et al.
- 2023
- ISCAS 2023
Analog In-Memory Computing for Deep Neural Network Acceleration
- - Andrea Fasoli
  - Geoffrey Burr
  - et al.
- 2023
- MRS Spring Meeting 2023
Analog-AI: Hardware Acceleration for Deep Neural Network Inference
- - Geoffrey Burr
  - Sidney Tsai
  - et al.
- 2023
- NeuMatDeCaS 2023
A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh
- - Shubham Jain
  - Hsinyu Tsai
  - et al.
- 2023
- IEEE Transactions on VLSI Systems
Impact of PCM noise on the Spiking Restricted Boltzmann Machine via On-Chip Trainable PCM synapses
- - Uicheol Shin
  - Masatoshi Ishii
  - et al.
- 2022
- MRS Fall Meeting 2022
Analog-memory-based 14nm Hardware Accelerator for Dense Deep Neural Networks including Transformers
- - Atsuya Okazaki
  - Pritish Narayanan
  - et al.
- 2022
- ISCAS 2022
Fully On-Chip MAC at 14 nm Enabled by Accurate Row-Wise Programming of PCM-Based Weights and Parallel Vector-Transport in Duration-Format
- - Pritish Narayanan
  - Stefano Ambrogio
  - et al.
- 2021
- IEEE T-ED
Fully on-chip MAC at 14nm enabled by accurate row-wise programming of PCM-based weights and parallel vector-transport in duration-format
- - P. Narayanan
  - S. Ambrogio
  - et al.
- 2021
- VLSI 2021
On-Chip Trainable 1.4M 6T2R PCM Synaptic Array with 1.6K Stochastic LIF Neurons for Spiking RBM
- - Masatoshi Ishii
  - U. Shin
  - et al.
- 2019
- IEDM 2019
Analysis of Effect of Weight Variation on SNN Chip with PCM-Refresh Method
- - A. Nomura
  - M. Ito
  - et al.
- 2019
- Neural Processing Letters

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Top collaborators

AO

Atsuya Okazaki

Atsuya Okazaki

Senior Research Scientist, IBM Research - Tokyo

VN

Vijay Narayanan

Vijay Narayanan

IBM Fellow, Semiconductor Pathfinding

ST

Sidney Tsai

Sidney Tsai

Manager, PRSM, AI Hardware and Cloud/AI for EDA

AN

Akiyo Nomura

Akiyo Nomura

Staff Research Scientist