Introducing the first sub-1 nanometer node chip — the smallest, most powerful chip technology in the world

When you boil down the last century of breakthroughs in computing, you’re left with something that almost feels closer to alchemy. We learned to shoot lightning at sand until it could do math. Over the decades, we learned to purify the silicon in the sand and turn it into transistors. Since then, the computers they power have revolutionized every facet of our lives. So much of our modern lives is powered by these infinitesimally small silicon devices that we have managed to shrink in size. The first transistor fit in the palm of your hand, and now the phone in your pocket contains tens of billions of transistors just in its central processor.

But as breakthroughs continue, as has the demand for compute power. AI and quantum computing are advancing at breakneck speed, and making us ask new questions of the devices we use.

That’s why today, IBM announced it's once again unveiling the smallest, most powerful computer chip technology in the world. These are the first sub-1 nanometer node chips, designed with transistor nodes that are just 0.7 nanometers, or 7 angstroms, wide. That makes them the smallest transistors in the world — by some margin. The team at IBM achieved this feat with several key breakthroughs in wafer bonding, SRAM scaling, and channel material innovation. 

To put this miniscule size into perspective, a human red blood cell is about 7,000 nanometers wide, or about 10,000 times larger than one of these new nodes. In a 7 angstrom chip the size of a fingernail, there are roughly 100 billion transistors. It’s the first time in human history that anyone has been able to pack that many transistors into a space this small.

These new IBM sub-1nm chips are 70% more efficient, or 50% more powerful, than the 2 nanometer node chips that IBM first unveiled back in 2021. Before today, those chips were still the smallest process node chips in the world.

With these sorts of power gains, the potential for 7 angstrom devices is sky high, with a massive potential impact on the world of AI. Today’s popular AI accelerators can produce about 1,500 TOPS (or trillions of operations per second), and IBM researchers estimate one using 7 angstrom technology could deliver about six times more, or around 9,000 TOPS. So if 7 angstrom chips were used to train today’s massive, frontier-model LLMs, we could drastically cut a typical training time from around three months to a couple weeks.

But these are just revolutions based on the technologies we use today. These 7 angstrom devices could unlock all sorts of innovations that we haven't even thought of yet. Any task that would benefit from considerably more processing power or energy-efficient chips could be on the table — from future autonomous machines that can do more on their own, to monitoring devices that would have to be recharged far less frequently.  

Nanostack: A new architecture for tomorrow’s chips

The new 7 angstrom design breakthrough is the result of building atop years of research at IBM. Back in 2015, IBM Research unveiled the nanosheet, a new chip architecture that researchers argued at the time would form the basis of the world’s chip designs for years to come. That came to pass with generation of chips created with 3 nm, and eventually 2 nm, nodes.

And there are still many years of evolutions with nanosheet ahead. It’ll be closer to the end of the decade before we see widescale adoption of 2 nm devices, which will be followed by 1.4 nm and 1nm devices after that. But IBM is always interested in inventing what’s next. That’s what led a team to explore what would come after nanosheets. Over the last few years, they’ve been working on how to pack more transistor density into a given space. Instead of just going smaller with two-dimension scaling, they wondered, what if you went taller in the third dimension? If innovations to date have been on the x- and y-axis, the team began to consider the z-axis.

This idea led to the intricate design that the team calls the nanostack. It’s the architecture powering the 7 angstrom breakthrough, and the team believes, at least a decade of silicon innovation.

The 7 angstrom chip, using the nanostack device architecture, was the result of breakthroughs in several key areas. The team was able to roughly double the density of transistors they could pack into a given space, when compared with 2 nm chips. The first major breakthrough is in thin dielectric wafer bonding. The team developed a new technique to bond two wafers to create a new, multilayered structure. The new method has proven to be sparse on defects, with the two wafers aligning as needed. The result is a true 3D transistor that in testing has shown to be extendable and scalable for a new generation of computer processors.

With the stacked transistors, the team can also leverage new materials for the channels in each node, maximizing the performance of each — independently of the other. The new staggered design for the field-effect transistors (or FETs) improves cell designs, and even shows the path for how to explore even smaller nodes in the future. Both the NFET and PFET channels have been optimized in a “gate stack” solution where the two channels can perform independently.

Finally, the team has managed to scale up SRAM (or static random-access memory) by 40% in the 7 angstrom design. It’s a massive leap in memory capacity — the likes of which the industry hasn’t seen in over a decade. Accessing on-chip memory is one of the key bottlenecks in AI computing that the team has addressed with the new 7 angstrom design, ensuring these chips will be able to process information much more rapidly than previous designs could. And by shrinking the physical footprint of memory, you can pack more capacity into the same amount of space.

As with all recent advances in transistor size, 7 angstroms refers to this new generation of chips, made with its specific manufacturing process. Here, 7 angstroms doesn’t correspond to the width of the contacted metal wires in the chip, as it traditionally did many generations ago when chips were much less dense. In general, a smaller process node technology produces smaller transistors. That means with each new generation, more transistors can be packed into a given space than their predecessor, making the chip faster and more energy efficient.

We see a pathway forward where this nanostack architecture could power multiple generations of transformative devices to come. This is the architecture to accelerate the Angstrom era. The potential for the future of computing, and the world, is immense. The sorts of questions that are intractable today could become effortless for future computers built on this architecture.