Preparing chip designers for the nanostack era

Earlier this year, IBM announced the world’s first 0.7nm node chip technology. Built on a totally redesigned transistor architecture that layers nanosheets on top of each other, the nanostack overcomes the spatial limitations of packing more transistors into a given footprint. In short, it unlocks the Z axis to reimagine logic scaling for the modern era. The result is nearly 100 billion transistors on a 150mm² chip, almost double the density of IBM’s 2nm node chip, with 50% better performance and 70% more energy efficiency, as well as 40% scaling in SRAM memory.

Now, as the semiconductor industry approaches this major transition in transistor architecture, IBM is announcing plans to make available an early research and development process design kit, or PDK, for the 7-angstrom nanostack technology in the first quarter of 2027. As the industry stands on the verge of this new era in semiconductor design, the PDK is intended to give organizations an early opportunity to explore how this emerging architecture can change their offerings.

A PDK provides the models, design rules, libraries, and other information engineers need to begin designing chips for a particular manufacturing process. IBM’s planned offering will help semiconductor companies evaluate nanostack technology well before it is ready for widespread adoption. Potential collaborators include fabless chip companies, electronic design automation (EDA) vendors, equipment suppliers, and research organizations interested in developing the technology.

“We want to invite people to work with us on the early PDK evaluation, and then on codifying the technology together,” said Jingyun Zhang, senior technology enablement manager at IBM Research.

Preparing for the future, together

IBM’s nanostack chip architecture represents a substantial departure from today’s nanosheet transistors. Instead of positioning n-type and p-type devices next to each other, the architecture stacks one above the other. This approach changes the physical layout of a circuit and introduces new considerations for resistance, capacitance, thermal behavior, and interactions between the upper and lower devices.

“The biggest difference is in the device structure,” Zhang said. “When people are trying to design a circuit now, they will need to shift their thinking from how things worked in the previous nanosheet generation, because the layout is changing from 2D to 3D at transistor level for the first time in logic foundry technology.”

The first version of the PDK is expected to include exemplary standard-cell libraries for logic functions and an exemplary SRAM design. Circuit designers will be able to use these resources to investigate placement and routing, produce early block-level layouts, and evaluate potential density and power-performance characteristics.

The initial release will not contain every model that a mature commercial PDK would include. Instead, it will advance collaborative research, establishing for the first time a foundation for design-technology co-optimization in a technology’s early phase on an open hardware innovation platform.

What’s next

For prospective partners, early access to the nanostack PDK offers more than a preview of a future transistor. It creates an opportunity to investigate how nanostack technology might be optimized for specific products. EDA companies can begin adapting their design tools to the architecture, while equipment makers can study the specialized fabrication challenges associated with its structure.

Researchers can also explore areas such as parasitic extraction, thermal coupling, and device-to-device interactions as the technology develops.

“The PDK will help people migrate from nanosheet to nanostack,” Zhang said. “We are standing at a point where we can help the industry get better prepared.”

Previous shifts — from planar transistors to FinFETs and from FinFETs to nanosheets — required the industry to rethink both fabrication and chip design. By making an early nanostack PDK available, IBM aims to give companies time to begin that process again, this time with an opportunity to help co-define the technology’s design ecosystem from the outset.