Publications

2 results at ISSCC 1990

Level-shifted and voltage-reduced 0.5 μm BiCMOS circuits
- - Chih-Liang Chen
- 1990
- ISSCC 1990
Conference paper
An 18 ns 56-bit multiply-adder circuit
- - Robert K. Montoye
  - P.W. Cook
  - et al.
- 1990
- ISSCC 1990
Conference paper

Level-shifted and voltage-reduced 0.5 μm BiCMOS circuits