A compact eFUSE programmable array memory for SOI CMOS
- John Safran
- Alan Leslie
- et al.
- 2007
- VLSI Circuits 2007
Publications
6 results at VLSI Circuits 2007
A 5.3GHz 8T-SRAM with operation down to 0.41V in 65nm CMOS
- Leland Chang
- Yutaka Nakamura
- et al.
- 2007
- VLSI Circuits 2007
A 2-GHz direct sampling delta-sigma tunable receiver with 40-GHz sampling clock and on-chip PLL
- T. Chalvatzis
- T.O. Dickson
- et al.
- 2007
- VLSI Circuits 2007
An 11 Gb/s 2.4 mW half-rate sampling 2-tap DFE receiver in 65nm CMOS
- Alexander Rylyakov
- 2007
- VLSI Circuits 2007
A sub-600mV, fluctuation tolerant 65nm CMOS SRAM array with dynamic cell biasing
- Azeez Bhavnagarwala
- Stephen Kosonocky
- et al.
- 2007
- VLSI Circuits 2007
A 75GHz PLL front-end integration in 65nm SOI CMOS technology
- Daeik Kim
- Jonghae Kim
- et al.
- 2007
- VLSI Circuits 2007