Publications

4 results at VLSI Circuits 2018

A 10-Bit 20-40 GS/S ADC with 37 dB SNDR at 40 GHz Input Using First Order Sampling Bandwidth Calibration
- - Lukas Kull
  - Danny Luu
  - et al.
- 2018
- VLSI Circuits 2018
Conference paper
A Scalable Multi-TeraOPS Deep Learning Processor Core for AI Trainina and Inference
- - Bruce Fleischer
  - Sunil Shukla
  - et al.
- 2018
- VLSI Circuits 2018
Conference paper
A 50GB/S 1.6PJ/B RX Data-Path with Quarter-Rate 3-Tap Speculative DFE
- - Pier Andrea Francese
  - Alessandro Cevrero
  - et al.
- 2018
- VLSI Circuits 2018
Conference paper
A 0.3PJ/Bit 112GB/S PAM4 1+0.5D TX-DFE Precoder and 8-Tap FFE in 14NM CMOS
- - Thomas Toifl
  - Christian Menolfi
  - et al.
- 2018
- VLSI Circuits 2018
Conference paper