Logic optimization by output phase assignment in dynamic logic synthesisR. PuriAndrew Bjorkstenet al.1996ICCAD 1996Conference paper
Inaccuracies in power estimation during logic synthesisD. BrandChandramouli Visweswariah1996ICCAD 1996Conference paper
Static timing analysis for self resetting circuitsV. NarayananB.A. Chappellet al.1996ICCAD 1996Conference paper
Optimization of custom MOS circuits by transistor sizingA.R. ConnP. Coulmanet al.1996ICCAD 1996Conference paper