Publications

141 results at IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Interval-valued reduced-order statistical interconnect modeling
- - James D. Ma
  - Rob A. Rutenbar
- 2007
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Path-based buffer insertion
- - C.N. Sze
  - Charles J. Alpert
  - et al.
- 2007
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Wire sizing for non-tree topology
- - Zhuo Li
  - Ying Zhou
  - et al.
- 2007
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Wire sizing for non-tree topology
- - Zhuo Li
  - Ying Zhou
  - et al.
- 2007
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Robust extraction of spatial correlation
- - Jinjun Xiong
  - Vladimir Zolotov
  - et al.
- 2007
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Heterogeneous behavioral hierarchy extensions for SystemC
- - Hiren D. Patel
  - Sandeep K. Shukla
  - et al.
- 2007
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Probabilistic transitive-closure ordering and its application on variational buffer insertion
- - Jinjun Xiong
  - Lei He
- 2007
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical timing for parametric yield prediction of digital integrated circuits
- - Jochen A. G. Jess
  - Kerim Kalafala
  - et al.
- 2006
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling and analysis of leakage currents in double-gate technologies
- - Saibal Mukhopadhyay
  - Keunwoo Kim
  - et al.
- 2006
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
First-order incremental block-based statistical timing analysis
- - Chandu Visweswariah
  - Kaushik Ravindran
  - et al.
- 2006
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems