Novel approach to reduce source/drain series resistance in high performance CMOS devices using self-aligned CoWP process for 45nm node UTSOI transistors with 20nm gate length
- James Pan
- Anna Topol
- et al.
- 2006
- VLSI Technology 2006
Publications
13 results at VLSI Technology 2006
Silicon-on-insulator MOSFETs with hybrid crystal orientations
- M. Yang
- K.K. Chan
- et al.
- 2006
- VLSI Technology 2006
Lower resistance scaled metal contacts to silicide for advanced CMOS
- A. Topol
- C. Sheraw
- et al.
- 2006
- VLSI Technology 2006