Generation of Performance Constraints for Layout
- Ravi Nair
- C. Leonard Berman
- et al.
- 1989
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Paper
Publications
141 results at IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal Aspect Ratios of Building Blocks in VLSI
- Shmuel Wimer
- Israel Koren
- et al.
- 1989
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PaperA New Framework of Design Rules for Compaction of VLSI Layouts
- Jin-Fuw Lee
- 1988
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PaperTRIM: Testability Range by Ignoring the Memory
- Larry Carter
- Leendert M. Huisman
- et al.
- 1988
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PaperAsymptotically Perfect Trivial Global Routing: A Stochastic Analysis
- Gregory B. Sorkin
- 1987
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PaperA Ranking Algorithm for MOS Circuit Layouts
- C. Andrew Neff
- Ravi Nair
- 1987
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PaperVLSI Layout Compaction with Grid and Mixed Constraints
- Jin-Fuw Lee
- Donald T. Tang
- 1987
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PaperHSS—A High-Speed Simulator
- Zeev Barzilai
- J. Lawrence Carter
- et al.
- 1987
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PaperOptimal Chaining of CMOS Transistors in a Functional Cell
- Shmuel Wimer
- Ron Y. Pinter
- et al.
- 1987
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PaperA Simple Yet Effective Technique for Global Wiring
- Ravi Nair
- 1987
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Paper