Complementary III-V heterojunction lateral NW Tunnel FET technology on Si
- D. Cutaia
- Kirsten E. Moselund
- et al.
- 2016
- VLSI Technology 2016
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117 results for Kirsten E. Moselund
Impact of trap-assisted tunneling and channel quantization on InAs/Si hetero Tunnel FETs
- Saurabh Sant
- Andreas Schenk
- et al.
- 2016
- DRC 2016
III-V-based hetero tunnel FETs: A simulation study with focus on non-ideality effects
- Andreas Schenk
- Saurabh Sant
- et al.
- 2016
- EUROSOI-ULIS 2016
III-V device integration on Si using template-assisted selective epitaxy
- Heinz Schmid
- Mattias Borg
- et al.
- 2015
- DRC 2015
Template-assisted selective epitaxy of III-V nanoscale devices for co-planar heterogeneous integration with Si
- Heinz Schmid
- Mattias Borg
- et al.
- 2015
- Applied Physics Letters
Comparative simulation study of InAs/Si and All-III-V hetero tunnel FETs
- Andreas Schenk
- Saurabh Sant
- et al.
- 2015
- ECS Meeting 2015 Chicago
Vertical InAs-Si gate-all-around tunnel FETs integrated on Si using selective epitaxy in nanotube templates
- D. Cutaia
- Kirsten E. Moselund
- et al.
- 2015
- IEEE J-EDS
Mechanisms of template-assisted selective epitaxy of InAs nanowires on Si
- Mattias Borg
- Heinz Schmid
- et al.
- 2015
- Journal of Applied Physics
Fabrication and analysis of vertical p-type InAs-Si nanowire tunnel FETs
- D. Cutaia
- Kirsten E. Moselund
- et al.
- 2015
- EUROSOI-ULIS 2015
III-V semiconductor nanowires for future devices
- Heinz Schmid
- Mattias Borg
- et al.
- 2014
- DATE 2014