A 7.5 GS/s flash ADC and a 10.24 GS/s time-interleaved ADC for backplane receivers in 65 nm CMOS
- Hayun Chung
- Zeynep Toprak-Deniz
- et al.
- 2015
- Analog Integr Circuits Signal Process
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23 results for Daniel Friedman
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology
- Timothy O. Dickson
- Yong Liu
- et al.
- 2015
- IEEE JSSC
A 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a ΔΣ noise-cancellation scheme
- Mark Ferriss
- Bodhisatwa Sadhu
- et al.
- 2015
- ISSCC 2015