Publications

3 results for Yutaka Nakamura

A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation
- - Gary S. Ditlow
  - Robert K. Montoye
  - et al.
- 2011
- ISSCC 2011
Conference paper
An 8T-SRAM for variability tolerance and low-voltage operation in high-performance caches
- - Leland Chang
  - Robert K. Montoye
  - et al.
- 2008
- IEEE Journal of Solid-State Circuits
Paper
A 5.3GHz 8T-SRAM with operation down to 0.41V in 65nm CMOS
- - Leland Chang
  - Yutaka Nakamura
  - et al.
- 2007
- VLSI Circuits 2007
Conference paper