Complete and effective robustness checking by means of interpolationStefan FrehseGorschwin Feyet al.2012FMCAD 2012
SAT-based synthesis of clock gating functions using 3-valued abstractionEli ArbelOleg Rokhlenkoet al.2009FMCAD 2009
Scalable conditional equivalence checking: An automated invariant-generation based approachJason BaumgartnerHari Monyet al.2009FMCAD 2009
Functional verification of power gated designs by compositional reasoningCindy EisnerAmir Nahiret al.2009Formal Methods in System Design