Publications

65 results for Effendi Leobandung

Opportunities and challenges of FinFET as a device structure candidate for 14nm node CMOS technology
- - Tenko Yamashita
  - Veeraraghvan S. Basker
  - et al.
- 2011
- CSTIC 2011
A 0.063 μm² FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch
- - Veeraraghvan S. Basker
  - Theodorus E. Standaert
  - et al.
- 2010
- VLSI Technology 2010
Ultra-thin-body and BOX (UTBB) Fully Depleted (FD) device integration for 22nm node and beyond
- - Q. Liu
  - A. Yagishita
  - et al.
- 2010
- VLSI Technology 2010
On the systematic analysis of ring-delay performance using statistical behavior model
- - Q. Liang
  - B. Greene
  - et al.
- 2009
- ISDRS 2009
High performance 32nm SOI CMOS with high-k/metal gate and 0.149μm ² SRAM and ultra low-k back end with eleven levels of copper
- - B. Greene
  - Q. Liang
  - et al.
- 2009
- VLSI Technology 2009
SMT and enhanced SPT with Recessed SD to improve CMOS Device Performance
- - S. Fang
  - S.S. Tan
  - et al.
- 2008
- ICSICT 2008
Recent progress and challenges in enabling embedded Si:C technology
- - B. Yang
  - Z. Ren
  - et al.
- 2008
- ECS Meeting 2008
(110) Channel, SiON gate-dielectric PMOS with record high I_on=1 mA/μm through channel stress and source drain external resistance (R _ext) engineering
- - B. Yang
  - A. Waite
  - et al.
- 2007
- IEDM 2007
A simple hardware-based statistical model on 65nm SOI CMOS technology
- - Q. Liang
  - J.B. Johnson
  - et al.
- 2007
- ISDRS 2007
Improving yields of high performance 65 nm chips with sputtering top surface of dual stress liner
- - Huilong Zhu
  - Daewon Yang
  - et al.
- 2007
- VLSI Technology 2007