An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS
- Mark Ferriss
- Jean-Olivier Plouchart
- et al.
- 2012
- VLSI Circuits 2012
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A 21.8-27.5GHz PLL in 32nm SOI using G m linearization to achieve -130dBc/Hz phase noise at 10MHz offset from a 22GHz carrier
- Bodhisatwa Sadhu
- Mark A. Ferriss
- et al.
- 2012
- RFIC 2012
Advanced modeling and optimization of high performance 32nm HKMG SOI CMOS for RF/analog SoC applications
- Sungjae Lee
- J. Johnson
- et al.
- 2012
- VLSI Technology 2012
Applications of SOI technologies to communication
- Jean-Olivier Plouchart
- 2011
- CSICS 2011
A 4GS/s, 8.45 ENOB and 5.7fJ/conversion, digital assisted, sampling system in 45nm CMOS SOI
- Mihai Sanduleanu
- Scott Reynolds
- et al.
- 2011
- CICC 2011
Exploiting combinatorial redundancy for offset calibration in flash ADCs
- Gokce Keskin
- Jonathan Proesel
- et al.
- 2011
- IEEE Journal of Solid-State Circuits
Bang-bang digital PLLS at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications
- A. Rylyakov
- J. Tierno
- et al.
- 2009
- ISSCC 2009
A low-power mm wave CML prescaler in 65nm SOI CMOS technology
- Daeik D. Kim
- Ongyeun Cho
- et al.
- 2008
- CSICS 2008
Wideband mmWave CML static divider in 65nm SOI CMOS technology
- Daeik D. Kim
- Ongyeun Cho
- et al.
- 2008
- CICC 2008
65nm SOI CMOS SoC technology for low-power mmwave and RF platform
- Daeik D. Kim
- Jonghae Kim
- et al.
- 2008
- SiRF 2008