Nanoscale CMOS circuit leakage power reduction By Double-gate device
- Keunwoo Kim
- Koushik K. Das
- et al.
- 2004
- ISLPED 2004
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51 results for Ching-Te Chuang
Simulation of nano-scale multi-fingered PD/SOI mosfets using the boltzmann transport equation
- José A. Pascual-Gutiérrez
- Jayathi Y. Murthy
- et al.
- 2004
- HT/FED 2004
New digital circuit techniques for total standby leakage reduction in nano-scale SOI technology
- Koushik K. Das
- Rajiv V. Joshi
- et al.
- 2003
- ESSCIRC 2003
Design and CAD Challenges in sub-90nm CMOS Technologies
- Kerry Bernstein
- Ching-Te Chuang
- et al.
- 2003
- ICCAD 2003
Effects of gate-to-body tunneling current on PD/SOI CMOS latches
- C.T. Chuang
- R. Puri
- 2003
- SISPAD 2003
New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology
- K. Das
- R.V. Joshi
- et al.
- 2003
- ISLPED 2003
New Optimal Design Strategies and Analysis of Ultra-Low Leakage Circuits for Nano-Scale SOI Technology
- Koushik K. Das
- Rajiv V. Joshi
- et al.
- 2003
- ISLPED 2003
Design considerations of scaled sub-0.1 μm PD/SOI CMOS circuits
- C.T. Chuang
- R.V. Joshi
- et al.
- 2003
- ISQED 2003
Effects of gate-to-body tunneling current on pass-transistor based PD/SOI CMOS circuits
- C.T. Chuang
- R. Puri
- 2002
- IEEE International SOI Conference 2002
Slew-rate monitoring circuit for on-chip process variation detection
- Amlan Ghosh
- Rahul M. Rao
- et al.
- 2013
- IEEE Transactions on VLSI Systems