Publications

64 results for J. Demarest

ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08μm² SRAM cell
- - Kangguo Cheng
  - A. Khakifirooz
  - et al.
- 2011
- VLSI Technology 2011
Impact of back bias on ultra-thin body and BOX (UTBB) devices
- - Q. Liu
  - Frederic Monsieur
  - et al.
- 2011
- VLSI Technology 2011
Sub-25nm FinFET with advanced fin formation and short channel effect engineering
- - Tenko Yamashita
  - Veeraraghvan S. Basker
  - et al.
- 2011
- VLSI Technology 2011
A 0.063 μm² FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch
- - Veeraraghvan S. Basker
  - Theodorus E. Standaert
  - et al.
- 2010
- VLSI Technology 2010
Challenges and solutions of extremely thin SOI (ETSOI) for CMOS scaling to 22nm node and beyond
- - Kangguo Cheng
  - Ali Khakifirooz
  - et al.
- 2010
- CSTIC 2010
Interactions of metal-organic PEALD TaN with ultra-low k dielectric materials
- - O. Van Der Straten
  - H. Shobha
  - et al.
- 2010
- ECS Transactions
Electromigration challenges for nanoscale Cu wiring
- - C.-K. Hu
  - L. Gignac
  - et al.
- 2008
- International Workshop on Stress-Induced Phenomena in Metallization 2008
The effect of a threshold failure time and bimodal behavior on the electromigration lifetime of copper interconnects
- - R. Filippi
  - P.-C. Wang
  - et al.
- 2009
- IRPS 2009
Copper contact metallization using Ru-based barrier liners for 45 nm and 32 nm nodes: Reliability and device performance
- - Soon-Cheon Seo
  - Chih-Chao Yang
  - et al.
- 2008
- ADMETA 2008
22 nm technology compatible fully functional 0.1 μm ² 6T-sram cell
- - B. Haran
  - A. Kumar
  - et al.
- 2008
- IEDM 2008